1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to a monolithic surface mount semiconductor optoelectronic device and fabrication method.
2. Description of the Prior Art
Some of the main issues driving component packaging today include thermal and electrical performance, real estate constraints (i.e., package size), and manufacturing cost. With integrated circuit (IC) geometry shrinking well into the sub-micron level, and operating frequencies in the gigahertz range, attention has focused on the evolution of advanced packaging technologies to address the numerous issues now plaguing diode, transistor, and IC designers. Ranging from thermal problems, to parasitic interference, to inductive losses, these issues have created a technological bottleneck, which has made packaging technology a crucial concern.
One of the basic limitations of semiconductor devices is the dissipation of heat that is generated during operation of the device. This heat must be transferred to a thermal sink without causing an excessive temperature rise within the device, which may cause partial or total device failure, and generally degrade the overall reliability of the device. The ability to dissipate heat places an upper bound on the maximum allowable power dissipation or ambient temperature range of operation for the device.
Where speed or power dissipation is not an issue, conventional plastic packages e.g., dual-in-line, surface mount, etc., which are typically non-hermetic and made of injection-molded epoxy compounds, are employed in the semiconductor industry due to their low cost. Plastic packages, however, inherently have higher parasitic capacitance and lower thermal conductivity, compared to other package types. Furthermore, conventional plastic package performance falls off or becomes widely erratic at higher frequencies (typically exceeding 1 gigahertz) due, at least in part, to variations in package parasitics (i.e., parasitic capacitance and inductance) from device to device. These and other disadvantages make standard plastic packages unsuitable for applications requiring high speed and high power dissipation.
Historically, where high speed and/or high power dissipation was a critical design requirement, expensive ceramic or metal can packages have been used, which generally exhibit lower parasitic capacitance, higher thermal conductivity, and greater mechanical strength than plastic packages. Aside from a substantially increased cost over standard plastic packages, ceramic and metal packages have an additional disadvantage of being bulkier than their plastic counterparts (i.e., larger in size) which is a detriment where circuit board real estate is scarce. Additionally, bonding wires, which connect the bond pads of the semiconductor device to the package pins, add series inductance, which significantly degrades the high frequency performance of the device.
Driven by the need for smaller consumer products and lower manufacturing costs, the trend has been to shrink the die and package size of circuit components. This is most evident, for example, in the cellular telephone market, which has recently pushed operating frequencies into the gigahertz range while concurrently shrinking the product size to easily fit in a shirt pocket. Because integrated circuit technology has resulted in increased functionality, enabling more circuit elements to be fabricated on the same semiconductor die, more heat is generated per unit volume within a smaller package footprint. Higher clock frequencies have further challenged the heat dissipation and speed capability of conventional package designs.
Although some heat generated by the semiconductor die is conveyed to the outside of the device package through the mold compound, the primary heat flow paths for a standard leadframe package are through the package leads themselves, which are typically made of copper. Unfortunately, conventional package leads and bond wires add significant amounts of parasitic inductance to the circuit. Although the length of the bond wires may be less for smaller package arrangements, the parasitic inductance associated with these bond wires is still significant at such frequencies, for example, in the gigahertz range. Therefore, high frequency performance remains substantially impaired. High-speed performance, high power dissipation, and small package size represent conflicting design requirements. Thus far, conventional integrated circuit packaging technology has failed to concurrently fulfill these important characteristics.
There are various other problems associated with conventional packaging technologies. For example, dwindling printed circuit board space has pressured semiconductor manufacturers to produce components having a smaller footprint (i.e., external package dimensions). Furthermore, quality, performance, reliability problems, and costly delays associated with offshore manufacturing e.g., assembly and packaging are additional concerns that prior art packaging technologies have failed to alleviate.
Substrates based on silicon carbide or sapphire provide good thermal conductivity, which is a significant aid in dissipating excessive heat away from the pn junction in an optoelectronic device, such as a light emitting diode (LED). However, sapphire wafers cost about $400 and silicon carbide wafers cost about $800.
In addition, the forward biased voltage requirement (Vf) for silicon carbide and sapphire substrates is nearly 4.0 volts. This voltage is difficult to supply in portable battery operated devices, such as handheld phones that only provide a maximum of about 3.9 volts when fully charged.
By focusing on only a single specific design problem, rather than addressing multiple problems simultaneously, prior art packaging technologies have exacerbated other equally crucial problems. Accordingly, there remains a need for a monolithic optoelectronic device integrated into a packaging arrangement that, among other things, is capable of high frequency operation, that can more readily dissipate the heat generated by the integrated circuit, that is smaller in physical size, that utilizes conventional semiconductor fabrication technology, that has modest voltage requirements, and that has a relatively low manufacturing cost.
It is an object of the present invention to provide a monolithic semiconductor device and method for fabricating the device that utilizes gallium nitride on a silicon substrate, which is more cost-effective than devices using either sapphire or silicon carbide substrates.
It is another object of the present invention to provide a monolithic semiconductor device and method for fabricating the device on larger substrates, such as those that are about 6-10 inches in diameter.
It is yet another object of the present invention to provide a monolithic semiconductor device and method for fabricating the device using packaging technology that overcomes inherent thermal conductivity problems by reducing a silicon substrate to a very thin layer of about 25-50 xcexcm.
It is still another object of the present invention to provide a monolithic semiconductor device and method for fabricating the device that is beneficial in battery powered devices by reducing the forward bias voltage requirements of light emitting diodes fabricated thereon.
It is a further object of the present invention to provide a monolithic semiconductor device and method for fabricating the device that is suitable for monolithic wafer level packaging, which is less expensive and more reliable than conventional metal ceramic packaging.
It is still a further object of the present invention to provide a monolithic semiconductor device and method for fabricating the device that enables on-wafer final testing and mapping for light output, which substantially reduces the overall cost of testing optoelectronic devices.
It is yet a further object of the present invention to provide a monolithic semiconductor device and method for fabricating the device that provides about 90-97% light transmission at a wavelength of about 450 nm, which is significantly more efficient than metal ceramic or epoxy packaging.
It is another object of the present invention to provide a monolithic semiconductor device and method for fabricating the device that enables simple phosphor coatings to be used to mix red, green, and blue light to make white light for use in liquid crystal displays.
A monolithic surface mount semiconductor process described in U.S. Pat. No. 6,187,611, which is incorporated herein by reference, is used to fabricate an optoelectronic device. A transparent epoxy layer and a glass layer offer excellent optical transmission characteristics and are used to cover the active surface of the optoelectronic device. The heat dissipation properties of the package, which are provided by thinned silicon vias, are advantageous for LED (light emitting diode) fabrication.
Prior art packaging technologies for conventional optoelectronic devices utilize wire bonding and die attach soldering of a chip into metal ceramic packages with some form of window or lens to enable the transmission of light outside the package. This process is relatively costly and has inherent reliability issues.
The subject invention utilizes an LED junction device that preferably outputs a characteristic wavelength of about 450 nm (blue light). The device is fabricated by growing a P+ layer, gallium nitride (GaN) layer, and a silicon (Si) GaN buffer layer on a 1:1:1 orientation silicon substrate. The buffer layer, which is preferably non-conductive, is made conductive by the addition of a metallic shorting ring connecting the gallium nitride layer through the N+ silicon substrate to one of two surface mount contacts. A conductive beam connects the buffer layer to the remaining surface mount contact via the N+ silicon substrate.